In order to simplify the description, in the remainder of this document we will limit ourselves to describe the special case of integrated circuits operating at a power supply voltage of 3V. Persons skilled in the art will easily extend this information to any type of voltage intended to supply power to an integrated electronic circuit.
In general, integrated circuits operate at a power supply voltage that is not perfectly stable, which sometimes causes serious damage when the power supply voltage drops to a very low level. For example, an under-powered microprocessor will operate unreliably, and could write corrupted data into a memory or overwrite programs, thus causing a system failure when the power supply voltage comes back to a normal level.
Therefore, it is conventional that an integrated circuit will include a Power Failure Detector (PFD) (also called a reset device in the remainder of the description) that generates a reset signal after detection of a drop in a power supply voltage so as to prevent working of the logic, memories or microprocessors until a sufficient power supply voltage is restored.
FIG. 1 shows a diagram of an example of a conventional power failure detector (PFD) referenced 10.
In the special case of this Figure, a first input 11411 of a differential amplifier 1141 powered by a power supply voltage VCC receives a voltage proportional to the power supply voltage VCC, called the weighted voltage div, and a second input 11412 receives a reference voltage VBGP. The differential amplifier 1141 generates a resultant voltage VDIFF on output 11413 that depends on the result of the comparison of the weighted voltage div and the reference voltage VBGP. The resultant voltage VDIFF is applied directly onto the gate GN1 of the transistor TN1. The transistor TN1, the source SN1 of which is connected to the reference potential VSS, and the drain DN1 of which is connected to a current source 111, is used like a switch 115, such that generation means 12 of a reset signal RST may or may not be activated depending on the value of the resultant voltage VDIFF.
In this solution, the generation means 12 are activated when the 3V power supply voltage VCC drops below a predetermined threshold of 2.4V. Indeed when the power supply voltage VCC is less than 2.4 V, the weighted voltage div, the value of which is equal to half of the power supply voltage VCC, is less than the reference voltage VBGP equal to 1.2 V. Therefore the differential amplifier 1141 generates a resultant voltage VDIFF on output 11413 that is equal to approximately the reference potential VSS, namely 0V, so that the transistor TN1 can be put in a non-conducting state (switch open), in which it directs the current ip2 from the current source 111 to the generation means 12, so as to activate the generation of a reset signal RST.
The power failure detector (PFD) 10 generally cooperates with an auxiliary device (not shown) for activating the means 12 of generating a reset signal RST. This auxiliary activation device (Power On Reset—POR) is typically produced using an RC filter and when the power failure detector (PFD) 10 is powered up, it activates the generation means 12 for a determined time until the power supply voltage VCC has increased to a sufficient level (>1.3V) to enable operation of the differential amplifier 1141.
The differential amplifier 1141 begins to operate as soon as the power supply voltage VCC reaches 1.1 V, at such a voltage this amplifier has a reaction time equal to approximately 50 μs. However, the differential amplifier 1141 cannot make a comparison until the power supply voltage VCC has reach 1.3 V, because no reference voltage VBGP is applied to the second input 11412 of the differential amplifier 1141. The BANDGAP cell 113 does not begin to output the reference voltage VBGP of 1.2 V until the power supply voltage VCC reaches 1.3 V.
This solution according to prior art has the disadvantage that it does not generate a reset signal when the power supply voltage drops to a very low level (power supply voltage less than 2.4V) quickly (in less than 1 μs).
This problem is usually overcome by adding a large capacitance (not shown) of several μF to the above-mentioned detector (PFD) 10. This capacitance is mounted outside the detector (PFD) 10, and slows the drop in the power supply voltage VCC. Thus, this technique enables the detector (PFD) 10 to generate a reset signal when the power supply voltage VCC drops to a level below 2.4 V and before it is too low (<1.3 V) to assure operation of the differential amplifier 1141.
However, this known technique has the disadvantage that it requires an expensive and large volume capacitance because it is not integrated in the printed circuit.